Imaging Sensor (3 Side Buttable)

For some imaging applications, such as medical X-ray imaging and satellite imaging, the detecting area has to be large and can only be covered by tiling several smaller detector units preferably in a 3-side buttable fashion, which poses many readout and addressing issues. The following novel STFC technology overcomes challenges posed by such a design.





The small feature size of modern CMOS processes limits the maximum area that can be exposed in one step to about 22 mm reticle size, but larger chips can be produced by breaking up the design into smaller sub-blocks that each fit into the reticle. It is more cost effective to repeat an identical design multiple times than to bring together multiple sub-blocks that are slightly different requiring different masks. In larger CMOS sensors it is therefore desirable to design a block of pixels which can be repeated identically to make up a larger pixel array. This can be achieved without difficulty if pixel addressing and readout are carried out from orthogonal sides of the array, but there is no current technology that allows the addressing and readout are to be carried out from the same side, to form a 3-side buttable design. In order to make the gaps (and hence unpixellated spaces) between the chips as small as possible it is desirable to carry out addressing and readout from the same side.


The invention outlined here solves both of the first two problems, whilst minimising image non-uniformity.

  • Firstly, the row addressing circuitry which would normally be placed along one side of the chip is moved to the bottom edge. Row selecting signals are then run up the chip and turned through 90 degrees to run to every pixel in a row. This allows pixels to extend to all three edges. This configuration, however, still causes a row to be selected in every stitching block, leading to corrupted data.
  • Secondly, special L-shaped lines are used from the logic at the bottom of the chip up through a stitching block. Because these lines are staggered, they effectively run diagonally across the chip. This means that if every stitching block connects to one of these lines at the same point, it is actually connected to a different signal at the bottom of the array.
  • Lastly, a single AND gate is placed on every row of the device with the two previously mentioned signals as its inputs. This combines two signals; one selecting the a row within a stitching block and another selecting a stitching block.


This AND gate does represent a slight variation in pixel layout, but intelligent placement of the gate will mitigate its effect. If the gates are distributed randomly, they will be almost invisible in the image, flat-field uniformity will be preserved. As the position of the gates is actually known and identical from one sensor to another, the distribution of gates will be called pseudo-random.



  • Placement of single AND gates using stitching block and row signals to select a single row.
  • Pseudo-random distribution of these gates to reduce their effect on image quality.



  • Standard stitching processes can be used.
  • All pixels have the same level of sensitivity.
  • Reduced power consumption.



  • Medical Physics (including Radiotherapy and Mammography)
  • Security
  • Any large field imaging application, e.g. focal plane arrays for telescopes
Patent Information:
Country Serial No.
Patent Cooperation Treaty PCT/GB2013/051911
United States 14/414217
For Information, Contact:
Elizabeth Bain
IP Manager
STFC Innovations
+44 (0) 1925 60 3680
01.a. Electronics
05.e. Meteorology/Climatology
06.a. Medicine, Human Health
10.a. Safety & Security